1. Field of the Invention
This invention relates to the field of semiconductor processing and, more particularly, to a transistor with an improved lightly doped drain ("LDD") structure and fabrication method for forming such a transistor.
2. Description of Relevant Art
Fabrication of a transistor is well-known. The manufacturing process begins by lightly doping a single crystal silicon substrate n-type or p-type. The specific area where the transistor will be formed is then isolated from other areas on the substrate with the use of isolation structures. In modern fabrication laboratories, the isolation structures may comprise shallow trenches in the substrate filled with dielectric oxide which acts as an insulator. Isolation structures may alternatively comprise, for example, locally oxidized silicon ("LOCOS") structures well known in the art. A gate dielectric may be formed by thermal oxidation of the silicon substrate; this oxidation might be performed in a thermal oxidation furnace or, alternatively, in a rapid thermal anneal ("RTA") apparatus. A gate conductor is then formed by depositing polycrystalline silicon upon the semiconductor topography and then doping it with an ion implant or a diffusion process. The gate structure is patterned using a mask followed by exposure, development, and etching. Subsequently, source and drain regions are doped, via ion implantation, with a high dosage n-type or p-type dopant. A channel region between the source and the drain is protected from the implant species by the pre-existing gate structure. When voltage above a certain threshold is applied to the gate of an enhancement-mode transistor, the channel between the source and drain becomes conductive and the transistor turns on.
As device dimensions are reduced while supply voltages remain constant (or are not reduced as rapidly as the structures are scaled), the maximum electric field becomes localized near the drain side of the channel causing acceleration of charge carriers toward the overlying gate oxide. The carriers become trapped in the gate oxide, a phenomenon generally called hot-carrier injection. The most harmful of its effects is damage inflicted to the gate dielectric and/or the substrate/gate dielectric interface. Over time, operational characteristics of the device may degrade due to hot-carried effects, that degradation resulting in, e.g., improper variation of threshold voltage, linear region transconductance, subthreshold slope, and saturation current. This may lead to the reduction of the lifetime of the devices. As a result, several techniques have been developed to combat this problem.
One set of methods involves making the gate dielectric and/or the gate substrate/dielectric interface more resistant to hot carriers. This can be accomplished by developing dielectric films that exhibit very low-density oxide trapping centers, interface state traps, and fixed oxide charge through special processing techniques. Reducing charge trapping opportunities, however, has given way to simply reducing the maximum electric field instead. Reducing the electric field in the drain-side channel or, more specifically, the maximum electric field is certainly a popular way to control hot-carrier effects. Reducing the electric field can be achieved by reducing the supply voltage of the device. However, this is not always possible due to operation voltage compatibility and other design reasons like noise levels. A common approach is to reduce the abruptness in voltage changes at the reverse-biased p-n junction at or near the drain side of the transistor channel. Disbursing abrupt voltage changes reduces the overall maximum electric field strength and the harmful hot-carrier effects resulting therefrom.
Reducing abrupt voltage changes can be accomplished by replacing an abrupt drain doping profile with a more gradually increasing lateral doping profile. A more gradual doping profile distributes the maximum electric field along a larger lateral distance such that the supply voltage is shared by the channel and the drain. Absent a more gradual doping profile, an abrupt junction can exist where almost all of the voltage drop occurs across the lightly-doped channel.
The simplest method to obtain a gradual doping at the drain-side channel is to use a dopant with a high diffusivity, for example, phosphorus instead of arsenic for an n-channel device. The faster-diffusing phosphorus readily migrates from its implant position in the drain toward the channel creating a gradually doped drain and consequently a smoother voltage profile. Unfortunately, however, the high diffusivity of phosphorus, in addition to creating a gradual lateral doping profile, also increases the lateral and vertical extents of the source and drain. Enlarging the source/drain junctions may bring about harmful short-channel effects and/or parasitic capacitances. Short-channel effects may result in less well-predicted threshold voltage, larger subthreshold currents, and altered IV characteristics.
For alleviating the hot carrier problem in short-channel transistors, a combination of phosphorus and arsenic may be used to form a double-diffused drain ("DDD"). Phosphorus and arsenic are co-implanted into the source and drain regions using two separate species: a medium dose of phosphorus (10.sup.14 -10.sup.15 ions/cm.sup.-2); and a heavy dose of arsenic (2-5.times.10.sup.15 ions/cm.sup.-2) may be used, for example. The faster-diffusing phosphorus naturally diffuses more than arsenic creating a less abrupt doping grading. Again such a doping grading reduces voltage abruptness that reduces the electric field in the channel region. The DDD structure is attractive because it adds little complexity to the process sequence. No extra masking steps are required; both dopants are implanted in sequence. Selecting the correct process and device parameters that yield an optimum DDD device, however, involves significant process and device calibration. Too much phosphorus will yield punchthrough problems, while not enough phosphorus will not provide adequate protection against hot-carrier effects.
The most widely-used device structure for increasing hot-carrier reliability is the lightly-doped drain ("LDD"). An LDD structure is made by a two-step implant process. The first step takes place after the formation of the gate. For an n-channel device, a relatively light implant of phosphorus or arsenic is used to form the lightly doped region adjacent the channel (i.e., the LDD implant). A conformal CVD oxide film is then deposited over the LDD implant and interposed gate. The oxide is then removed using an anisotropic dry-etch process. Anisotropic etch removes oxide in the substantially horizontal regions, leaving what are known as "spacers" on the sides of the gate. After the oxide spacers are formed, a second implant occurs at a higher dosage than the first implant. The second implant is chosen to use the same implant "type" (i.e., n or p) as the first. It is masked from areas adjacent the gate by virtue of the pre-existing oxide spacers. Using an n-type example, the first implant may use phosphorus, while the second uses arsenic. The oxide spacers serve to mask the high dose arsenic and to offset it from the gate edges. By introducing the spacers after the LDD implant, the LDD structure offers more freedom in optimizing the LDD implant area than the DDD structure. The LDD area is controlled by the lateral spacer dimension and the thermal drive cycle, and is made independent from the source and drain implant (second implant) depth. The conventional LDD process, however, sacrifices some device performance to improve hot-carrier resistance. For example, the LDD process exhibits reduced drive current under comparable gate and source voltages.
LDD structures are well versed at reducing the abruptness of voltage across the reversed-biased drain-channel junction. Still, however, the doping profile in this critical area near the drain is not necessarily a smooth one. In addition, conventional LDD structures in n-channel devices typically use phosphorus which has a high diffisivity. Any subsequent thermal processing will cause the phosphorus atoms to migrate laterally into the channel or vertically into the substrate. As mentioned above, migration enhances unwanted parasitic problems or short-channel effects. Migration of dopants over time will also alter many transistor characteristics beyond their allowed tolerances. Such alteration will limit device lifetimes significantly.